Abstract: | In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, quantum computing and nanotechnology. Low power circuits implemented using reversible logic that provides single error correction – double error detection (SEC-DED) is proposed in this paper. The design is done using a new 4 x 4 reversible gate called ‘HCG’ for implementing hamming error coding and detection circuits. A parity preserving HCG (PPHCG) that preserves the input parity at the output bits is used for achieving fault tolerance for the hamming error coding and detection circuits. |
Description: | TENCON 2007-2007 IEEE Region 10 Conference |
URI: | http://dyuthi.cusat.ac.in/purl/3859 |
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Fault Tolerant ... ng and Detection using.pdf | (168.5Kb) |
Abstract: | Speech signals are one of the most important means of communication among the human beings. In this paper, a comparative study of two feature extraction techniques are carried out for recognizing speaker independent spoken isolated words. First one is a hybrid approach with Linear Predictive Coding (LPC) and Artificial Neural Networks (ANN) and the second method uses a combination of Wavelet Packet Decomposition (WPD) and Artificial Neural Networks. Voice signals are sampled directly from the microphone and then they are processed using these two techniques for extracting the features. Words from Malayalam, one of the four major Dravidian languages of southern India are chosen for recognition. Training, testing and pattern recognition are performed using Artificial Neural Networks. Back propagation method is used to train the ANN. The proposed method is implemented for 50 speakers uttering 20 isolated words each. Both the methods produce good recognition accuracy. But Wavelet Packet Decomposition is found to be more suitable for recognizing speech because of its multi-resolution characteristics and efficient time frequency localizations |
Description: | Advances in Computing and Communications (ICACC), 2012 International Conference on |
URI: | http://dyuthi.cusat.ac.in/purl/3888 |
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Feature Extract ... ken Words in Malayalam.pdf | (261.9Kb) |
Abstract: | Treating e-mail filtering as a binary text classification problem, researchers have applied several statistical learning algorithms to email corpora with promising results. This paper examines the performance of a Naive Bayes classifier using different approaches to feature selection and tokenization on different email corpora |
Description: | International Journal of Computer Science and Communication Vol. 3, No. 1, January-June 2012, pp. 81-84 |
URI: | http://dyuthi.cusat.ac.in/purl/3915 |
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FEATURE SELECTI ... TEXT OF SPAM FILTERING.pdf | (402.6Kb) |
Abstract: | Decimal multiplication is an integral part of financial, commercial, and internet-based computations. A novel design for single digit decimal multiplication that reduces the critical path delay and area for an iterative multiplier is proposed in this research. The partial products are generated using single digit multipliers, and are accumulated based on a novel RPS algorithm. This design uses n single digit multipliers for an n × n multiplication. The latency for the multiplication of two n-digit Binary Coded Decimal (BCD) operands is (n + 1) cycles and a new multiplication can begin every n cycle. The accumulation of final partial products and the first iteration of partial product generation for next set of inputs are done simultaneously. This iterative decimal multiplier offers low latency and high throughput, and can be extended for decimal floating-point multiplication. |
Description: | Parallel and Distributed Processing with Applications, 2008. ISPA'08. International Symposium on |
URI: | http://dyuthi.cusat.ac.in/purl/3874 |
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Fixed Point Dec ... on using RPS Algorithm.pdf | (424.3Kb) |
Abstract: | Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that offers low latency and high throughput. This design performs two digit multiplications simultaneously in one clock cycle. Double digit fixed point decimal multipliers for 7digit, 16 digit and 34 digit are simulated using Leonardo Spectrum from Mentor Graphics Corporation using ASIC Library. The paper also presents area and delay comparisons for these fixed point multipliers on Xilinx, Altera, Actel and Quick logic FPGAs. This multiplier design can be extended to support decimal floating point multiplication for IEEE 754- 2008 standard. |
Description: | Nature & Biologically Inspired Computing, 2009. NaBIC 2009. World Congress on |
URI: | http://dyuthi.cusat.ac.in/purl/3873 |
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High Performanc ... Multiplier on ASIC and.pdf | (164.5Kb) |
Abstract: | Biometrics has become important in security applications. In comparison with many other biometric features, iris recognition has very high recognition accuracy because it depends on iris which is located in a place that still stable throughout human life and the probability to find two identical iris's is close to zero. The identification system consists of several stages including segmentation stage which is the most serious and critical one. The current segmentation methods still have limitation in localizing the iris due to circular shape consideration of the pupil. In this research, Daugman method is done to investigate the segmentation techniques. Eyelid detection is another step that has been included in this study as a part of segmentation stage to localize the iris accurately and remove unwanted area that might be included. The obtained iris region is encoded using haar wavelets to construct the iris code, which contains the most discriminating feature in the iris pattern. Hamming distance is used for comparison of iris templates in the recognition stage. The dataset which is used for the study is UBIRIS database. A comparative study of different edge detector operator is performed. It is observed that canny operator is best suited to extract most of the edges to generate the iris code for comparison. Recognition rate of 89% and rejection rate of 95% is achieved |
Description: | Computer Science & Information Technology (CS & IT) |
URI: | http://dyuthi.cusat.ac.in/purl/3906 |
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IRIS BIOMETRIC ... PLOYING CANNY OPERATOR.pdf | (667.4Kb) |
Abstract: | This paper describes JERIM-320, a new 320-bit hash function used for ensuring message integrity and details a comparison with popular hash functions of similar design. JERIM-320 and FORK -256 operate on four parallel lines of message processing while RIPEMD-320 operates on two parallel lines. Popular hash functions like MD5 and SHA-1 use serial successive iteration for designing compression functions and hence are less secure. The parallel branches help JERIM-320 to achieve higher level of security using multiple iterations and processing on the message blocks. The focus of this work is to prove the ability of JERIM 320 in ensuring the integrity of messages to a higher degree to suit the fast growing internet applications |
Description: | International Journal of Computer Science and Applications, Vol. 5, No. 4, pp 11 - 25, 2008 |
URI: | http://dyuthi.cusat.ac.in/purl/4021 |
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Jerim-320 A New ... With Parallel Branches.pdf | (96.80Kb) |
Abstract: | Cooperative caching in mobile ad hoc networks aims at improving the efficiency of information access by reducing access latency and bandwidth usage. Cache replacement policy plays a vital role in improving the performance of a cache in a mobile node since it has limited memory. In this paper we propose a new key based cache replacement policy called E-LRU for cooperative caching in ad hoc networks. The proposed scheme for replacement considers the time interval between the recent references, size and consistency as key factors for replacement. Simulation study shows that the proposed replacement policy can significantly improve the cache performance in terms of cache hit ratio and query delay |
Description: | Advance Computing Conference (IACC), 2013 IEEE 3rd International |
URI: | http://dyuthi.cusat.ac.in/purl/3885 |
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A key based cac ... mobile ad hoc networks.pdf | (177.3Kb) |
Abstract: | Cooperative caching is an attractive solution for reducing bandwidth demands and network latency in mobile ad hoc networks. Deploying caches in mobile nodes can reduce the overall traffic considerably. Cache hits eliminate the need to contact the data source frequently, which avoids additional network overhead. In this paper we propose a data discovery and cache management policy for cooperative caching, which reduces the caching overhead and delay by reducing the number of control messages flooded in to the network. A cache discovery process based on location of neighboring nodes is developed for this. The cache replacement policy we propose aims at increasing the cache hit ratio. The simulation results gives a promising result based on the metrics of studies |
Description: | Advanced Infocomm Technology (ICAIT), 2013 6th International Conference on |
URI: | http://dyuthi.cusat.ac.in/purl/3900 |
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A Location Aide ... Mobile Ad hoc Networks.pdf | (254.6Kb) |
Abstract: | The focus of this work is to provide authentication and confidentiality of messages in a swift and cost effective manner to suit the fast growing Internet applications. A nested hash function with lower computational and storage demands is designed with a view to providing authentication as also to encrypt the message as well as the hash code using a fast stream cipher MAJE4 with a variable key size of 128-bit or 256-bit for achieving confidentiality. Both nested Hash function and MAJE4 stream cipher algorithm use primitive computational operators commonly found in microprocessors; this makes the method simple and fast to implement both in hardware and software. Since the memory requirement is less, it can be used for handheld devices for security purposes. |
Description: | Advanced Computing and Communications, 2006. ADCOM 2006. International Conference on |
URI: | http://dyuthi.cusat.ac.in/purl/3881 |
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Message Integri ... d a Fast Stream Cipher.pdf | (1.288Mb) |
Abstract: | Cluster based protocols like LEACH were found best suited for routing in wireless sensor networks. In mobility centric environments some improvements were suggested in the basic scheme. LEACH-Mobile is one such protocol. The basic LEACH protocol is improved in the mobile scenario by ensuring whether a sensor node is able to communicate with its cluster head. Since all the nodes, including cluster head is moving it will be better to elect a node as cluster head which is having less mobility related to its neighbours. In this paper, LEACH-Mobile protocol has been enhanced based on a mobility metric “remoteness” for cluster head election. This ensures high success rate in data transfer between the cluster head and the collector nodes even though nodes are moving. We have simulated and compared our LEACH-Mobile-Enhanced protocol with LEACHMobile. Results show that inclusion of neighbouring node information improves the routing protocol. |
Description: | ADCOM 2008 |
URI: | http://dyuthi.cusat.ac.in/purl/3857 |
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Mobility Metric based LEACH-Mobile Protocol.pdf | (272.3Kb) |
Abstract: | A new fast stream cipher, MAJE4 is designed and developed with a variable key size of 128-bit or 256-bit. The randomness property of the stream cipher is analysed by using the statistical tests. The performance evaluation of the stream cipher is done in comparison with another fast stream cipher called JEROBOAM. The focus is to generate a long unpredictable key stream with better performance, which can be used for cryptographic applications. |
Description: | INDICON, 2005 Annual IEEE |
URI: | http://dyuthi.cusat.ac.in/purl/3865 |
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A New Fast Stream Cipher MAJE4.pdf | (1.449Mb) |
Abstract: | Reversibility plays a fundamental role when logic gates such as AND, OR, and XOR are not reversible. computations with minimal energy dissipation are considered. Hence, these gates dissipate heat and may reduce the life of In recent years, reversible logic has emerged as one of the most the circuit. So, reversible logic is in demand in power aware important approaches for power optimization with its circuits. application in low power CMOS, quantum computing and A reversible conventional BCD adder was proposed in using conventional reversible gates. |
Description: | System-on-Chip, 2007 International Symposium on |
URI: | http://dyuthi.cusat.ac.in/purl/3863 |
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A new look at r ... ation of decimal adder.pdf | (344.1Kb) |
Abstract: | Cooperative caching is used in mobile ad hoc networks to reduce the latency perceived by the mobile clients while retrieving data and to reduce the traffic load in the network. Caching also increases the availability of data due to server disconnections. The implementation of a cooperative caching technique essentially involves four major design considerations (i) cache placement and resolution, which decides where to place and how to locate the cached data (ii) Cache admission control which decides the data to be cached (iii) Cache replacement which makes the replacement decision when the cache is full and (iv) consistency maintenance, i.e. maintaining consistency between the data in server and cache. In this paper we propose an effective cache resolution technique, which reduces the number of messages flooded in to the network to find the requested data. The experimental results gives a promising result based on the metrics of studies. |
Description: | David C. Wyld (Eds) : ICCSEA, SPPR, CSIA, WimoA - 2013 pp. 203–209, 2013. © CS & IT-CSCP 2013 |
URI: | http://dyuthi.cusat.ac.in/purl/3886 |
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A Novel Cache R ... reless Mobile Networks.pdf | (130.7Kb) |
Abstract: | A novel and fast technique for cryptographic applications is designed and developed using the symmetric key algorithm “MAJE4” and the popular asymmetric key algorithm “RSA”. The MAJE4 algorithm is used for encryption / decryption of files since it is much faster and occupies less memory than RSA. The RSA algorithm is used to solve the problem of key exchange as well as to accomplish scalability and message authentication. The focus is to develop a new hybrid system called MARS4 by combining the two cryptographic methods with an aim to get the advantages of both. The performance evaluation of MARS4 is done in comparison with MAJE4 and RSA. |
Description: | India Conference, 2006 Annual IEEE |
URI: | http://dyuthi.cusat.ac.in/purl/3909 |
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A Novel Fast Hybrid Cryptographic System MARS4.pdf | (191.8Kb) |
Abstract: | Animportant step in the residue number system(RNS) based signal processing is the conversion of signal into residue domain. Many implementations of this conversion have been proposed for various goals, and one of the implementations is by a direct conversion from an analogue input. A novel approach for analogue-to-residue conversion is proposed in this research using the most popular Sigma–Delta analogue-to-digital converter (SD-ADC). In this approach, the front end is the same as in traditional SD-ADC that uses Sigma–Delta (SD) modulator with appropriate dynamic range, but the filtering is doneby a filter implemented usingRNSarithmetic. Hence, the natural output of the filter is an RNS representation of the input signal. The resolution, conversion speed, hardware complexity and cost of implementation of the proposed SD based analogue-to-residue converter are compared with the existing analogue-to-residue converters based on Nyquist rate ADCs |
Description: | International Journal of Electronics Vol. 96, No. 6, June 2009, 571–583 |
URI: | http://dyuthi.cusat.ac.in/purl/4020 |
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A novel Sigma–D ... e-to-residue converter.pdf | (707.5Kb) |
Abstract: | In this paper we investigate the problem of cache resolution in a mobile peer to peer ad hoc network. In our vision cache resolution should satisfy the following requirements: (i) it should result in low message overhead and (ii) the information should be retrieved with minimum delay. In this paper, we show that these goals can be achieved by splitting the one hop neighbours in to two sets based on the transmission range. The proposed approach reduces the number of messages flooded in to the network to find the requested data. This scheme is fully distributed and comes at very low cost in terms of cache overhead. The experimental results gives a promising result based on the metrics of studies. |
Description: | International Journal of Wireless & Mobile Networks (IJWMN) Vol. 5, No. 5, October 2013 |
URI: | http://dyuthi.cusat.ac.in/purl/3903 |
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PEER TO PEER CA ... MOBILE AD HOC NETWORKS.pdf | (146.0Kb) |
Abstract: | Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that performs 2 digit multiplications simultaneously in one clock cycle. This design offers low latency and high throughput. When multiplying two n-digit operands to produce a 2n-digit product, the design has a latency of (n / 2) 1 cycles. The paper presents area and delay comparisons for 7-digit, 16-digit, 34-digit double digit decimal multipliers on different families of Xilinx, Altera, Actel and Quick Logic FPGAs. The multipliers presented can be extended to support decimal floating-point multiplication for IEEE P754 standard |
Description: | Programmable Logic, 2009. SPL. 5th Southern Conference on |
URI: | http://dyuthi.cusat.ac.in/purl/3867 |
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PERFORMANCE ANA ... MULTIPLIER ON VARIOUS.pdf | (300.0Kb) |
Abstract: | Residue Number System (RNS) based Finite Impulse Response (FIR) digital filters and traditional FIR filters. This research is motivated by the importance of an efficient filter implementation for digital signal processing. The comparison is done in terms of speed and area requirement for various filter specifications. RNS based FIR filters operate more than three times faster and consumes only about 60% of the area than traditional filter when number of filter taps is more than 32. The area for RNS filter is increasing at a lesser rate than that for traditional resulting in lower power consumption. RNS is a nonweighted number system without carry propogation between different residue digits.This enables simultaneous parallel processing on all the digits resulting in high speed addition and multiplication in the RNS domain |
Description: | Communications and Information Technologies, 2007. ISCIT'07. International Symposium on |
URI: | http://dyuthi.cusat.ac.in/purl/3861 |
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Performance ana ... RNS versus traditional.pdf | (257.8Kb) |
Abstract: | This paper presents a performance analysis of reversible, fault tolerant VLSI implementations of carry select and hybrid decimal adders suitable for multi-digit BCD addition. The designs enable partial parallel processing of all digits that perform high-speed addition in decimal domain. When the number of digits is more than 25 the hybrid decimal adder can operate 5 times faster than conventional decimal adder using classical logic gates. The speed up factor of hybrid adder increases above 10 when the number of decimal digits is more than 25 for reversible logic implementation. Such highspeed decimal adders find applications in real time processors and internet-based applications. The implementations use only reversible conservative Fredkin gates, which make it suitable for VLSI circuits. |
Description: | Proceedings of the World Congress on Engineering and Computer Science 2007 WCECS 2007, October 24-26, 2007, San Francisco, USA |
URI: | http://dyuthi.cusat.ac.in/purl/3891 |
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Performance Ana ... le Fast Decimal Adders.pdf | (402.4Kb) |
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