| dc.contributor.author |
Poulose Jacob,K |
|
| dc.contributor.author |
Rekha, James K |
|
| dc.contributor.author |
Sreela Sasi |
|
| dc.date.accessioned |
2014-06-11T06:15:45Z |
|
| dc.date.available |
2014-06-11T06:15:45Z |
|
| dc.date.issued |
2009-04-01 |
|
| dc.identifier.uri |
http://dyuthi.cusat.ac.in/purl/3867 |
|
| dc.description |
Programmable Logic, 2009. SPL. 5th Southern Conference on |
en_US |
| dc.description.abstract |
Decimal multiplication is an integral part of financial,
commercial, and internet-based computations. This paper
presents a novel double digit decimal multiplication
(DDDM) technique that performs 2 digit multiplications
simultaneously in one clock cycle. This design offers low
latency and high throughput. When multiplying two n-digit
operands to produce a 2n-digit product, the design has a
latency of (n / 2) 1 cycles. The paper presents area
and delay comparisons for 7-digit, 16-digit, 34-digit double
digit decimal multipliers on different families of Xilinx,
Altera, Actel and Quick Logic FPGAs. The multipliers
presented can be extended to support decimal floating-point
multiplication for IEEE P754 standard |
en_US |
| dc.description.sponsorship |
Cochin University of Science and Technology |
en_US |
| dc.language.iso |
en |
en_US |
| dc.publisher |
IEEE |
en_US |
| dc.subject |
Decimal Multipliers |
en_US |
| dc.subject |
FPGA |
en_US |
| dc.subject |
Carry Save Adders |
en_US |
| dc.title |
Performance analysis of double digit decimal multiplier on various FPGA logic families |
en_US |
| dc.type |
Article |
en_US |