Poulose Jacob,K; Shahana, T K; Sasi, S; Rekha, James K(IEEE, November 21, 2005)
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Abstract:
This paper presents a new approach to implement
Reed-Muller Universal Logic Module (RM-ULM)
networks with reduced delay and hardware for
synthesizing logic functions given in Reed-Muller (RM)
form. Replication of single control line RM-ULM is
used as the only design unit for defining any logic
function. An algorithm is proposed that does exhaustive
branching to reduce the number of levels and modules
required to implement any logic function in RM form.
This approach attains a reduction in delay, and power
over other implementations of functions having large
number of variables.