Poulose Jacob,K; Shahana, T K; Rekha, James K; Sreela Sasi(IEEE, December 1, 2008)
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Abstract:
Decimal multiplication is an integral part offinancial,
commercial, and internet-based computations. The basic
building block of a decimal multiplier is a single digit
multiplier. It accepts two Binary Coded Decimal (BCD)
inputs and gives a product in the range [0, 81] represented
by two BCD digits. A novel design for single digit decimal
multiplication that reduces the critical path delay and area
is proposed in this research. Out of the possible 256
combinations for the 8-bit input, only hundred
combinations are valid BCD inputs. In the hundred valid
combinations only four combinations require 4 x 4
multiplication, combinations need x multiplication,
and the remaining combinations use either x or x
3 multiplication. The proposed design makes use of this
property. This design leads to more regular VLSI
implementation, and does not require special registers for
storing easy multiples. This is a fully parallel multiplier
utilizing only combinational logic, and is extended to a
Hex/Decimal multiplier that gives either a decimal output
or a binary output. The accumulation ofpartial products
generated using single digit multipliers is done by an array
of multi-operand BCD adders for an (n-digit x n-digit)
multiplication.
Description:
Electronic Design, 2008. ICED 2008. International Conference on
Poulose Jacob,K; Sreela Sasi; Shahana, T K; Rekha, James K(IEEE, December 10, 2008)
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[-]
Abstract:
Decimal multiplication is an integral part of
financial, commercial, and internet-based
computations. A novel design for single digit decimal
multiplication that reduces the critical path delay and
area for an iterative multiplier is proposed in this
research. The partial products are generated using
single digit multipliers, and are accumulated based on
a novel RPS algorithm. This design uses n single digit
multipliers for an n × n multiplication. The latency for
the multiplication of two n-digit Binary Coded Decimal
(BCD) operands is (n + 1) cycles and a new
multiplication can begin every n cycle. The
accumulation of final partial products and the first
iteration of partial product generation for next set of
inputs are done simultaneously. This iterative decimal
multiplier offers low latency and high throughput, and
can be extended for decimal floating-point
multiplication.
Description:
Parallel and Distributed Processing with Applications, 2008. ISPA'08. International Symposium on