Palson,T I; Dr.Joy, George(Cochin University Of Science And Technology, February 16, 1987)
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Abstract:
The work reported in this thesis is the preparation,
and the structural, electrical and optical properties
of reactively evaporated lead sulphide and tin telluride
thin films. The three temperature method had been used
for the preparation of these semiconductor thin films.
In this preparation technique constituent elements are
evaporated from separate sources with the substrate kept
at a particular temperature. when one of the constituent
element is a gas near room temperature, the method is
often called reactive evaporation. It has been found for
many materials that a stoichiometric interval exists with
a limited range of flux and substrate temperature. Usually
this technique is used for the preparation of thin films of
high melting point compounds or of materials which decompose
during evaporation. Tin telluride and lead sulphide are
neither high melting point materials nor do they decompose
on melting. But even than reactive evaporation offers the
possibility of changing the ratios of the flux of the constituent
elements within a wide range and studying its
effect on the properties of the films
Description:
Department of Physics, Cochin
University of Science and Technology
Anu, Philip; Dr. Rajeev Kumar, K(Cochin University of Science and Technology, December , 2011)
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Abstract:
Present work deals with the Preparation and characterization of high-k aluminum oxide thin films by atomic layer deposition for gate dielectric applications.The ever-increasing demand for functionality and speed for semiconductor applications requires enhanced performance, which is achieved by the continuous miniaturization of CMOS dimensions. Because of this miniaturization, several parameters, such as the dielectric thickness, come within reach of their physical limit. As the required oxide thickness approaches the sub- l nm range, SiO 2 become unsuitable as a gate dielectric because its limited physical thickness results in excessive leakage current through the gate stack, affecting the long-term reliability of the device. This leakage issue is solved in the 45 mn technology node by the integration of high-k based gate dielectrics, as their higher k-value allows a physically thicker layer while targeting the same capacitance and Equivalent Oxide Thickness (EOT). Moreover, Intel announced that Atomic Layer Deposition (ALD) would be applied to grow these materials on the Si substrate. ALD is based on the sequential use of self-limiting surface reactions of a metallic and oxidizing precursor. This self-limiting feature allows control of material growth and properties at the atomic level, which makes ALD well-suited for the deposition of highly uniform and conformal layers in CMOS devices, even if these have challenging 3D topologies with high aspect-ratios.
ALD has currently acquired the status of state-of-the-art and most preferred deposition technique, for producing nano layers of various materials of technological importance. This technique can be adapted to different situations where precision in thickness and perfection in structures are required, especially in the microelectronic scenario.
Description:
Department of Instrumentation,
Cochin University of Science and Technology