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Please use this identifier to cite or link to this item: http://purl.org/purl/3891

Title: Performance Analysis of Reversible Fast Decimal Adders
Authors: Poulose Jacob,K
Sreela Sasi
Rekha, James K
Shahana, T K
Keywords: decimal arithmetic
delay reduction
reversible logic
VLSI implementation
Issue Date: Oct-2007
Publisher: International Conference on Computer Science and Applications
Abstract: This paper presents a performance analysis of reversible, fault tolerant VLSI implementations of carry select and hybrid decimal adders suitable for multi-digit BCD addition. The designs enable partial parallel processing of all digits that perform high-speed addition in decimal domain. When the number of digits is more than 25 the hybrid decimal adder can operate 5 times faster than conventional decimal adder using classical logic gates. The speed up factor of hybrid adder increases above 10 when the number of decimal digits is more than 25 for reversible logic implementation. Such highspeed decimal adders find applications in real time processors and internet-based applications. The implementations use only reversible conservative Fredkin gates, which make it suitable for VLSI circuits.
Description: Proceedings of the World Congress on Engineering and Computer Science 2007 WCECS 2007, October 24-26, 2007, San Francisco, USA
URI: http://dyuthi.cusat.ac.in/purl/3891
Appears in Collections:Dr. K Poulose Jacob

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