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Browsing by Author Sasi, S

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Issue Date	Title	Author(s)
21-Nov-2005	Automated synthesis of delay-reduced Reed-Muller universal logic module networks	Poulose Jacob,K; Shahana, T K; Sasi, S; Rekha, James K
17-Oct-2007	Performance analysis of FIR digital filter design: RNS versus traditional	Poulose Jacob,K; Shahana, T K; James, R K; Jose, B R; Sasi, S
18-Dec-2007	Quick Addition of Decimals Using Reversible Conservative Logic	Poulose Jacob,K; Rekha, James K; Shahana, T K; Sasi, S

Showing results 1 to 3 of 3