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Browsing by Author Rekha, James K
Showing results 7 to 15 of 15
Preview | Issue Date | Title | Author(s) | | 9-Dec-2009 | High performance, low latency double digit decimal multiplier on ASIC and FPGA | Poulose Jacob,K; Sreela Sasi; Rekha, James K |
| 4-Jun-2013 | An Improved Design of Combinational Digital Circuits with Multiplexers using Genetic Algorithm | Mythili, P; Dileep, Lukose; Vijayakumari, C K; Rekha, James K |
| 20-Nov-2007 | A new look at reversible logic implementation of decimal adder | Poulose Jacob,K; Rekha, James K; Shahana, T K; Sreela Sasi |
| 1-Apr-2009 | Performance analysis of double digit decimal multiplier on various FPGA logic families | Poulose Jacob,K; Rekha, James K; Sreela Sasi |
| Oct-2007 | Performance Analysis of Reversible Fast Decimal Adders | Poulose Jacob,K; Sreela Sasi; Rekha, James K; Shahana, T K |
| 2007 | Polyphase Implementation of Non-recursive Comb Decimators for Sigma-Delta A/D Converters | Poulose Jacob,K; Rekha, James K; Babita, Jose R; Shahana, T K; Sreela Sasi |
| 18-Dec-2007 | Quick Addition of Decimals Using Reversible Conservative Logic | Poulose Jacob,K; Rekha, James K; Shahana, T K; Sasi, S |
| 11-May-2008 | RNS based programmable multi-mode decimation filter for WCDMA and WiMAX | Poulose Jacob,K; Rekha, James K; Sreela Sasi; Shahana, T K; Babita, Jose R |
| 12-Dec-2008 | RRNS-convolutional encoded concatenated code for OFDM based wireless communication | Poulose Jacob,K; Shahana, T K; Sreela Sasi; Rekha, James K; Babita, Jose R |
Showing results 7 to 15 of 15
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