A novel Sigma–Delta based parallel analogue-to-residue converter

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A novel Sigma–Delta based parallel analogue-to-residue converter

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dc.contributor.author Poulose Jacob,K
dc.contributor.author Shahana, T K
dc.contributor.author Babita, Jose R
dc.contributor.author Sreela Sasi
dc.date.accessioned 2014-07-15T05:31:02Z
dc.date.available 2014-07-15T05:31:02Z
dc.date.issued 2009-05-01
dc.identifier.issn 0020-7217 print/ISSN 1362-3060 online
dc.identifier.uri http://dyuthi.cusat.ac.in/purl/4020
dc.description International Journal of Electronics Vol. 96, No. 6, June 2009, 571–583 en_US
dc.description.abstract Animportant step in the residue number system(RNS) based signal processing is the conversion of signal into residue domain. Many implementations of this conversion have been proposed for various goals, and one of the implementations is by a direct conversion from an analogue input. A novel approach for analogue-to-residue conversion is proposed in this research using the most popular Sigma–Delta analogue-to-digital converter (SD-ADC). In this approach, the front end is the same as in traditional SD-ADC that uses Sigma–Delta (SD) modulator with appropriate dynamic range, but the filtering is doneby a filter implemented usingRNSarithmetic. Hence, the natural output of the filter is an RNS representation of the input signal. The resolution, conversion speed, hardware complexity and cost of implementation of the proposed SD based analogue-to-residue converter are compared with the existing analogue-to-residue converters based on Nyquist rate ADCs en_US
dc.description.sponsorship Cochin University of Science and Technology en_US
dc.language.iso en en_US
dc.publisher Taylor & Francis en_US
dc.subject analogue-to-residue converter en_US
dc.subject Sigma–Delta modulator en_US
dc.subject decimation filter en_US
dc.subject residue number system en_US
dc.subject performance evaluation en_US
dc.title A novel Sigma–Delta based parallel analogue-to-residue converter en_US
dc.type Article en_US


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