Antimedian graphs are introduced as the graphs in which for every triple
of vertices there exists a unique vertex x that maximizes the sum of the
distances from x to the vertices of the triple. The Cartesian product of
graphs is antimedian if and only if its factors are antimedian. It is proved
that multiplying a non-antimedian vertex in an antimedian graph yields
a larger antimedian graph. Thin even belts are introduced and proved to
be antimedian. A characterization of antimedian trees is given that leads
to a linear recognition algorithm.
Bank switching in embedded processors having partitioned memory architecture results in code size as well as run time overhead. An algorithm and its application to assist the compiler in eliminating the redundant bank switching codes introduced and deciding the optimum data allocation to banked memory is presented in this work. A relation matrix formed for the memory bank state transition corresponding to each bank selection instruction is used for the detection of redundant codes. Data allocation to memory is done by considering all possible permutation of memory banks and combination of data. The compiler output corresponding to each data mapping scheme is subjected to a static machine code analysis which identifies the one with minimum number of bank switching codes. Even though the method is compiler independent, the algorithm utilizes certain architectural features of the target processor. A prototype based on PIC 16F87X microcontrollers is described. This method scales well into larger number of memory blocks and other architectures so that high performance compilers can integrate this technique for efficient code generation. The technique is illustrated with an example
Description:
International Journal of Software Engineering and Its Applications
Vol. 6, No. 1, January, 2012
Mythili, P; Dileep, Lukose; Vijayakumari, C K; Rekha, James K(IEEE, June 4, 2013)
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Abstract:
This paper presents a new approach to the design of
combinational digital circuits with multiplexers using
Evolutionary techniques. Genetic Algorithm (GA) is used as the
optimization tool. Several circuits are synthesized with this
method and compared with two design techniques such as
standard implementation of logic functions using multiplexers
and implementation using Shannon’s decomposition technique
using GA. With the proposed method complexity of the circuit
and the associated delay can be reduced significantly
Description:
International Conference on Microelectronics, Communication and Renewable Energy (ICMiCR-2013)