Poulose Jacob,K; Sreela Sasi; Shahana, T K; Rekha, James K(IEEE, December 10, 2008)
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Abstract:
Decimal multiplication is an integral part of
financial, commercial, and internet-based
computations. A novel design for single digit decimal
multiplication that reduces the critical path delay and
area for an iterative multiplier is proposed in this
research. The partial products are generated using
single digit multipliers, and are accumulated based on
a novel RPS algorithm. This design uses n single digit
multipliers for an n × n multiplication. The latency for
the multiplication of two n-digit Binary Coded Decimal
(BCD) operands is (n + 1) cycles and a new
multiplication can begin every n cycle. The
accumulation of final partial products and the first
iteration of partial product generation for next set of
inputs are done simultaneously. This iterative decimal
multiplier offers low latency and high throughput, and
can be extended for decimal floating-point
multiplication.
Description:
Parallel and Distributed Processing with Applications, 2008. ISPA'08. International Symposium on