Poulose Jacob,K; Sreela Sasi; Rekha, James K; Shahana, T K(International Conference on Computer Science and Applications, October , 2007)
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Abstract:
This paper presents a performance analysis of
reversible, fault tolerant VLSI implementations of carry select
and hybrid decimal adders suitable for multi-digit BCD
addition. The designs enable partial parallel processing of all
digits that perform high-speed addition in decimal domain.
When the number of digits is more than 25 the hybrid decimal
adder can operate 5 times faster than conventional decimal
adder using classical logic gates. The speed up factor of hybrid
adder increases above 10 when the number of decimal digits is
more than 25 for reversible logic implementation. Such highspeed
decimal adders find applications in real time processors
and internet-based applications. The implementations use only
reversible conservative Fredkin gates, which make it suitable for
VLSI circuits.
Description:
Proceedings of the World Congress on Engineering and Computer Science 2007
WCECS 2007, October 24-26, 2007, San Francisco, USA
Poulose Jacob,K; Rekha, James K; Shahana, T K; Sasi, S(IEEE, December 18, 2007)
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Abstract:
In recent years, reversible logic has emerged as one
of the most important approaches for power
optimization with its application in low power CMOS,
nanotechnology and quantum computing. This research
proposes quick addition of decimals (QAD) suitable for
multi-digit BCD addition, using reversible conservative
logic. The design makes use of reversible fault tolerant
Fredkin gates only. The implementation strategy is to
reduce the number of levels of delay there by increasing
the speed, which is the most important factor for high
speed circuits.
Description:
Advanced Computing and Communications, 2007. ADCOM 2007. International Conference on