Poulose Jacob,K; Sreela Sasi; Rekha, James K(IEEE, December 9, 2009)
[+]
[-]
Abstract:
Decimal multiplication is an integral part of
financial, commercial, and internet-based computations.
This paper presents a novel double digit decimal
multiplication (DDDM) technique that offers low latency
and high throughput. This design performs two digit
multiplications simultaneously in one clock cycle. Double
digit fixed point decimal multipliers for 7digit, 16 digit and
34 digit are simulated using Leonardo Spectrum from
Mentor Graphics Corporation using ASIC Library. The
paper also presents area and delay comparisons for these
fixed point multipliers on Xilinx, Altera, Actel and Quick
logic FPGAs. This multiplier design can be extended to
support decimal floating point multiplication for IEEE 754-
2008 standard.
Description:
Nature & Biologically Inspired Computing, 2009. NaBIC 2009. World Congress on